v0.2.540814.9 MB
unset
strict
core18
SystemVerilog language server
A language server supporting SystemVerilog ( IEEE Std. 1800-2017 )
Update History
v0.2.5 (408)13 Dec 2025, 09:47 UTC
15 Nov 2019, 05:58 UTC
18 Aug 2022, 07:47 UTC
13 Dec 2025, 09:47 UTC